A liquid crystal display device includes a scan signal line driving circuit and a data signal line driving circuit, each of which includes a shift resister for generating a signal for sequentially driving pixels in an array arrangement. Further, the liquid crystal display device also includes: a level shifter for converting a power supply voltage level; and a buffer which has a low output impedance and outputs an amplification signal in a broad sense, such as an amplification circuit for outputting a signal which is 100%-amplified with respect to an input signal. In a case where a CMOS transistor is used to constitute a semiconductor device, such as the shift resister or the buffer, processes for forming a p-channel and an n-channel, respectively, would be required, thereby complicating a manufacturing process for the semiconductor device. Therefore, for the sake of a simple manufacturing process for the semiconductor device, it is preferable to use a transistor of a same conductivity type, such as a unipolar-channel-type transistor (e.g. a transistor having the p-channel only). For example, Patent Literature 1 discloses a semiconductor device constituted by such unipolar transistors.
FIG. 46 is a circuit diagram illustrating an arrangement of the semiconductor device disclosed in Patent Literature 1. This semiconductor device is constituted by n-type MOS transistors.
Specifically, the semiconductor device 100 includes four n-type MOS transistors T101 to T104, and a capacitor C101. The transistor T101 is arranged such that its drain terminal is connected to a power supply VDD, and its gate terminal is connected to an input terminal IN. The transistor T103 is arranged such that its source terminal is connected to a power supply VSS, and its gate terminal receives a STOP signal (control signal). The transistor T102 is arranged such that its drain terminal is connected to a clock terminal φ, and its gate terminal is connected to (i) a source terminal of the transistor T101, and (ii) a drain terminal of the transistor T103. The transistor T104 is arranged such that (i) its drain terminal is connected to a source terminal of the transistor T102, (ii) its source terminal is connected to the power supply VSS, and (iii) its gate terminal is connected to the gate terminal of the transistor T103. A connection point between the transistors T101, T102, and T103 is a node N1, and a connection point between the transistors T102 and T104 is a node N2. The capacitor C101 is provided between the nodes N1 and N2. The node N2 is connected to an output terminal OUT.
Next, the following description explains an operation of the semiconductor device 100. FIG. 47 is a timing chart showing waveforms of various signals of the semiconductor device 100.
When an input signal IN switches to a high level, the transistor T101 is turned on, and an electric potential at the node N1 increases to “VDD−Vth (where Vth is a threshold voltage of the transistor T101)” (pre-charge operation). As the electric potential at the node N1 increases, the transistor T102 is turned on. Here, in a case where a clock signal φ is being at a low level, a signal being at the low level is outputted from the output terminal OUT. Once an electric charge is pre-charged, the electric potential at the node N1 is retained until the STOP signal turns into an active state (high level) (floating state). If the clock signal φ switches to the high level in this floating state, the electric potential at the node N1 is boosted by an electric potential of α to “VDD−Vth+α” due to the capacitor C101 (bootstrap operation). During a period of time in which this electric potential is being greater than “VDD+Vth”, a signal having an electric potential level of VDD is outputted from the output terminal OUT.
Then, when the STOP signal switches to the high level, the electric potential at the node N1 is discharged to VSS by the transistor T103, so that the transistor T102 is turned off. The transistor T104 is turned on, so that a signal having an electric potential level of VSS is outputted from the output terminal OUT.
Thus, with the arrangement of the conventional semiconductor device, it is possible to output a signal having a high electric potential, with a simple circuit arrangement by taking advantage of the bootstrap operation. Therefore, it is possible to use such a semiconductor device suitably in sections in a liquid crystal display device.